1. Field of the Invention
The invention relates to a method for fabricating isolation regions in semiconductor devices, and more particularly, to a method for reducing stress between the nitride and poly layers and the dimension of the bird's beak without necessitating the removal of the polysilicon buffer layer.
2. Description of the Prior Art
Isolation regions among semiconductor devices that prevent the individual device from operation interference by others have become a very important technique, especially given the increases of the packing densities of semiconductor devices. One common isolation scheme is to apply a local oxidation of silicon (LOCOS) process to fabricate such isolation regions. Typically, the LOCOS process utilizes the property of oxygen diffusion through Si.sub.3 N.sub.4 (silicon nitride) that is patterned on the substrate to form field oxide regions. Accordingly, oxide thermally grows at the substrate surface that is not covered by the silicon nitride.
Basically, the isolation regions formed by the conventional LOCOS process usually suffers from bird's beak, which is a lateral extension of the field oxide (isolation region) into the active area of the semiconductor device. Some disadvantages of the LOCOS process made itself unsuitable for deep sub-micro technologies. Except for the aforementioned bird's beak, non-planarization, oxide field-thinning effect, and stress-induced defects still remain problems which need to be overcome. New isolation schemes are thus sequentially suggested to overcome the disadvantages of the LOCOS process. For example, poly-buffered LOCOS (PBL or PBLOCOS) is a widely adopted LOCOS-based process that substantially reduces the dimension of the undesirable bird's beak.
Unfortunately, the PBL approach still suffers from pit problems induced by voids that occur in the polysilicon layer during field oxide growth. It is proposed that the voids arise from stress between the nitride and poly layers. On the other hand, no matter the LOCOS-based schemes are modified, it seems difficult to reduce the bird's beak length to much less than 0.1 micro-meter. Another isolation technology, the shallow-trench isolation process, is thus disclosed for sub-quarter-micro-meter technology. Generally, dry etching is performed to anisotropically etch the substrate by using a sacrificial photoresist layer as mask. Next, when a chemical-vapor-deposition (CVD) oxide layer is deposited on the substrate surface, an etching back process is performed to leave only the top surface at the same level as the original substrate. Obviously, neither bird's beak nor encroachment is obtained in the isolation region.
Although the shallow-trench isolation brings advantages that are insufficient in the LOCOS-based process, the shallow-trench isolation is nevertheless a more complicated process than all of the LOCOS-based methods. Accordingly, the shallow-trench isolation has not been broadly used in industry. Some articles are consecutively disclosed to suggest methods for overcoming the aforementioned disadvantages of the LOCOS-based processes. For example, an article titled "Characteristics of CMOS device isolation for the ULSI age" (referring to IDEM p. 679, 1994) disclosed by Bryant et al. suggests a method for overcoming the problem between the LOCOS and the shallow trench isolation processes to achieve a scaling requirement. Nagal et al. disclose in an article titled "Stress-induced void formation in interlevel polysilicon films during polybuffered local oxidation of silicon" in J. of Electrochem (vol. 140, p. 2356, 1993) a method that eliminates the pit problem of the polysilicon buffer layer after a wet etching is performed. It is obvious that current isolation schemes have not as yet achieved the requirements of the semiconductor devices. A need has arisen to disclose an isolation method for improving known isolation methods, and furthermore, to overcome the disadvantages of conventional skills.